82G33 datasheet(164/437 Pages) INTEL

164 / 437 page

DRAM Controller Registers (D0:F0)

164

Datasheet

Bit

Access &

Default

Description

25:22

0000b

DRAM Refresh Hysterisis (REFHYSTERISIS): Hysterisis level -

Useful for dref_high watermark cases. The dref_high flag is set when

the dref_high watermark level is exceeded, and is cleared when the

refresh count is less than the hysterisis level. This bit should be set to

a value less than the high watermark level.

0000 = 0

0001 = 1

.......

1000 = 8

21:18

0000b

DRAM Refresh High Watermark (REFHIGHWM): When the

refresh count exceeds this level, a refresh request is launched to the

scheduler and the dref_high flag is set.

0000 = 0

0001 = 1

.......

1000 = 8

17:14

0000b

DRAM Refresh Low Watermark (REFLOWWM): When the refresh

count exceeds this level, a refresh request is launched to the

scheduler and the dref_low flag is set.

0000 = 0

0001 = 1

.......

1000 = 8

13:0

001100001

10000b

Refresh Counter Time Out Value (REFTIMEOUT): Program this

field with a value that will provide 7.8 us at the memory clock

frequency. At various memory clock frequencies this results in the

following values:

266 MHz -> 820 hex

333 MHz -> A28 hex

400 MHz -> C30 hex

533 MHz -> 104B hex

666 MHz -> 1450 hex

82G33 Datasheet(PDF) 164 Page - Intel Corporation

82G33 Datasheet(HTML) 164 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL