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82G33 Datasheet(PDF) 167 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 167 Page - Intel Corporation

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DRAM Controller Registers (D0:F0)
Datasheet
167
Bit
Access &
Default
Description
Note: During boot, all other thermometer mode registers (except
lock bits) should be programmed appropriately before enabling
the Thermometer Mode.
Clock used is the memory command clock (i.e., ep_mcclk).
Note: The same legacy thermal sensor design in prior (G)MCHs has
been used in this design. However, the thermal sensor logic
runs in a memory command clock domain that is ½ the
frequency of the memory clock used in prior designs. Hence
the period counted for the thermal sensor settling time has
doubled for the same settings, compared to prior (G)MCHs.
Thus the thermal sensor programming should be updated to
maintain the same thermometer rate count as in prior
(G)MCHs.
Lockable via TCO bit 7.
0000 = Thermometer mode disabled (i.e., analog sensor mode)
0001 = enabled, 512 clock mode
0010 = enabled, 1024 clock mode
(normal Thermometer mode operation, for DDR 667/800)
provides ~6.14 us settling time @ 167 MHz ep_mcclk (DDR 667)
provides ~5.12 us settling time @ 200 MHz ep_mcclk (DDR 800)
provides ~3.84 us settling time @ 267 MHz ep_mcclk (DDR 1066)
0011 = enabled, 1536 clock mode
(normal Thermometer mode operation, for DDR 1066)
provides ~9.22 us settling time @ 167 MHz ep_mcclk (DDR 667)
provides ~7.68 us settling time @ 200 MHz ep_mcclk (DDR 800)
provides ~5.76 us settling time @ 267 MHz ep_mcclk (DDR 1066)
provides ~4.61 us settling time @ 333 MHz ep_mcclk (DDR 1333)
0100 = enabled, 2048 clock mode
(normal Thermometer mode operation, for DDR 1333)
provides ~15.36 us settling time @ 133 MHz ep_mcclk (DDR 533)
provides ~12.29 us settling time @ 167 MHz ep_mcclk (DDR 667)
provides ~10.24 us settling time @ 200 MHz ep_mcclk (DDR 800)
provides ~7.68 us settling time @ 267 MHz ep_mcclk (DDR 1066)
0101 = enabled, 3072 clock mode
0110 = enabled, 4096 clock mode
0111 = enabled, 6144 clock mode
all other permutations are reserved
1111 = enabled, 4 clock mode (for testing digital logic)
NOTE: The settling time for DAC and Thermal Diode is between 2 and
5 us. To meet this requirement the SE value must be
programmed to be 5 us or more. Recommendation is to use:
“0010” setting for DDR 667/800 and “0011” setting for DDR
1066.



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