82G33 datasheet(165/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

165

5.2.42

TSC1—Thermal Sensor Control 1

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

CD8h

Default Value:

00h

Access:

RW/L, RW, RS/WC

Size:

8 bits

This register controls the operation of the thermal sensor. Bits 7:1 of this register are

reset to their defaults by CL_PWROK. Bit 0 is reset to its default by PLTRST#.

Bit

Access &

Default

Description

RW/L

Thermal Sensor Enable (TSE): This bit enables power to the

thermal sensor. Lockable via TCO bit 7.

0 = Disabled

1 = Enabled

Analog Hysteresis Control (AHC): This bit enables the analog

hysteresis control to the thermal sensor. When enabled, about 1

degree of hysteresis is applied. This bit should normally be off in

thermometer mode since the thermometer mode of the thermal

sensor defeats the usefulness of analog hysteresis.

0 = hysteresis disabled

1= analog hysteresis enabled.

5:2

0000b

Digital Hysteresis Amount (DHA): This bit determines whether no

offset, 1 LSB, 2... 15 is used for hysteresis for the trip points.

0000 = digital hysteresis disabled, no offset added to trip

temperature

0001 = offset is 1 LSB added to each trip temperature when tripped

...

0110 = ~3.0 °C (Recommended setting)

...

1110 = added to each trip temperature when tripped

1111 = added to each trip temperature when tripped

RW/L

Thermal Sensor Comparator Select (TSCS): This bit multiplexes

between the two analog comparator outputs. Normally Catastrophic is

used. Lockable via TCO bit 7.

0 = Catastrophic

1 = Hot

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