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82G33 Datasheet(PDF) 161 Page - Intel Corporation |
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82G33 Datasheet(HTML) 161 Page - Intel Corporation |
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161 / 437 page  DRAM Controller Registers (D0:F0) Datasheet 161 Bit Access & Default Description 13 RW 0b EPDunit Power Down enable for ODT Rank (EPDOAPDEN): Configuration to enable the ODT ranks to dynamically enter power down. 1 = Enable active power down. 0 = Disable active power down. 12 RW 0b EPDunit Power Down enable for Active Rank (EPDAAPDEN): Configuration to enable the active rank to dynamically enter power down. 1 = Enable active power down. 0 = Disable active power down. 11:10 RO 0h Reserved 9:1 RW 00000000 0b Self refresh exit count (sd0_cr_slfrfsh_exit_cnt): This field indicates the Self refresh exit count. (Program to 255) 0 RW 0b indicates only 1 rank enabled (sd0_cr_singledimmpop): This field indicates that only 1 rank is enabled. This bit needs to be set if there is one active rank and no odt ranks, or if there is one active rank and one odt rank and they are the same rank. |
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