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82G33 Datasheet(PDF) 137 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 137 Page - Intel Corporation

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DRAM Controller Registers (D0:F0)
Datasheet
137
5.2.10
C0CYCTRKWR—Channel 0 CYCTRK WR
B/D/F/Type:
0/0/0/MCHBAR
Address Offset:
256–257h
Default Value:
0000h
Access:
RW
Size:
16 bits
This register provides Channel 0 CYCTRK WR.
Bit
Access &
Default
Description
15:12
RW
0h
ACT To Write Delay (C0sd_cr_act_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the ACT and
WRITE commands to the same rank-bank. This field corresponds to
tRCD_wr in the DDR Specification.
11:8
RW
0h
Same Rank Write To Write Delay (C0sd_cr_wrsr_wr): This field
indicates the minimum allowed spacing (in DRAM clocks) between two
WRITE commands to the same rank.
7:4
RW
0h
Different Rank Write to Write Delay (C0sd_cr_wrdr_wr): This
field indicates the minimum allowed spacing (in DRAM clocks)
between two WRITE commands to different ranks. This field
corresponds to tWR_WR in the DDR Specification.
3:0
RW
0h
READ To WRTE Delay (C0sd_cr_rd_wr): This field indicates the
minimum allowed spacing (in DRAM clocks) between the READ and
WRITE commands. This field corresponds to tRD_WR.



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