82G33 datasheet(135/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

135

5.2.7

C0DRA23—Channel 0 DRAM Rank 2,3 Attribute

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

20A–20Bh

Default Value:

0000h

Access:

R/W

Size:

16 bits

See C0DRA01 register for programming information.

Bit

Access &

Default

Description

15:8

R/W

00h

Channel 0 DRAM Rank-3 Attributes (CODRA3): This register

defines DRAM pagesize/number-of-banks for rank3 for given channel.

See Table 5-3 for programming.

7:0

R/W

00h

Channel 0 DRAM Rank-2 Attributes (CODRA2): This register

defines DRAM pagesize/number-of-banks for rank2 for given channel.

See Table 5-3 for programming.

5.2.8

C0CYCTRKPCHG—Channel 0 CYCTRK PCHG

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

250–251h

Default Value:

0000h

Access:

RW, RO

Size:

16 bits

This register provides Channel 0 CYCTRK Precharge.

Bit

Access &

Default

Description

15:11

00000b

Reserved

10:6

00000b

Write To PRE Delayed (C0sd_cr_wr_pchg): This field indicates the

minimum allowed spacing (in DRAM clocks) between the WRITE and

PRE commands to the same rank-bank. This field corresponds to tWR in

the DDR Specification.

5:2

0000b

READ To PRE Delayed (C0sd_cr_rd_pchg): This field indicates the

minimum allowed spacing (in DRAM clocks) between the READ and PRE

commands to the same rank-bank.

1:0

00b

PRE To PRE Delayed (C0sd_cr_pchg_pchg): This field indicates the

minimum allowed spacing (in DRAM clocks) between two PRE

commands to the same rank.

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