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82G33 Datasheet(PDF) 126 Page - Intel Corporation |
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82G33 Datasheet(HTML) 126 Page - Intel Corporation |
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126 / 437 page ![]() DRAM Controller Registers (D0:F0) 126 Datasheet Bit Access & Default Description 38 RO 0b DDR3 Disable (DDR3D): 0 = Capable of supporting DDR3 SDRAM (82G33 GMCH and 82P35 MCH only) 1 = Not Capable of supporting DDR3 SDRAM 37:34 RO 0000b Reserved 33:31 RO 000b DDR Frequency Capability (DDRFC): This field controls which values may be written to the Memory Frequency Select field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h). Any attempt to write an unsupported value will be ignored. 000 = (G)MCH capable of "All" memory frequencies 001 = Reserved 010 = Reserved 011 = (G)MCH capable of up to DDR2/DDR3 1333 100 = (G)MCH capable of up to DDR2/DDR3 1067 101 = (G)MCH capable of up to DDR2/DDR3 800 110 = (G)MCH capable of up to DDR2/DDR3 667 NOTE: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components. 30:28 RO 000b FSB Frequency Capability (FSBFC): This field controls which values are allowed in the PSB Frequency Select Field 2:0 of the Clocking Configuration Register. These values are determined by the BSEL[2:0] frequency straps. Any unsupported strap values will render the (G)MCH System Memory Interface inoperable. 000 = (G)MCH capable of "All" Memory Frequencies 001 = Reserved 010 = Reserved 011 = (G)MCH capable of up to PSB 1333 100 = (G)MCH capable of up to PSB 1067 101 = (G)MCH capable of up to PSB 800 110 = (G)MCH capable of up to PSB 667 27:24 RO 1h CAPID Version (CAPIDV): This field has the value 0001b to identify the first revision of the CAPID register definition. 23:16 RO 0bh CAPID Length (CAPIDL): This field has the value 0bh to indicate the structure length (11 bytes). 15:8 RO 00h Next Capability Pointer (NCP): This field is hardwired to 00h indicating the end of the capabilities linked list. 7:0 RO 09h Capability Identifier (CAP_ID): This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for vendor dependent capability pointers. |
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