82G33 datasheet(124/437 Pages) INTEL

124 / 437 page

DRAM Controller Registers (D0:F0)

124

Datasheet

Bit

Access &

Default

Description

2 DIMMS per Channel Disable (2DPCD):

0 = 2 DIMMs per channel Enabled

1 = 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3

of the rank population field for each channel to zero. (MCHBAR

offset 260h, bits 22–23 for channel 0 and MCHBAR offset 660h,

bits 22–23 for channel 1)

75:73

00b

Reserved

Agent Presence Disable (APD):

0 = Disable

1 = Enable

System Defense Disable (CBD):

0 = Disable

1 = Enable

Multiprocessor Disable (MD):

0 = (G)MCH capable of Multiple Processors

1 = (G)MCH capable of uni-processor only.

FAN Speed Control Disable (FSCD):

0 = Disable

1 = Enable

EastFork Disable (EFD):

0 = Disable

1 = Enable

67:58

Reserved

ME Disable (MED):

0 = ME feature is enabled

1 = ME feature is disabled

56:48

Reserved

82Q35, 82Q33, 82G33 GMCH

3D Integrated graphics Disable (3DIGD):

0 = 3D Internal Graphics are enabled

1 = 3D Internal Graphics are disabled. VGA still supported

82P35 MCH

Reserved

82G33 Datasheet(PDF) 124 Page - Intel Corporation

82G33 Datasheet(HTML) 124 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL