82G33 datasheet(120/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

120

Datasheet

Bit

Access &

Default

Description

RWC/S

Isochronous TBWRR Run behind FIFO put (ITSTV):

If set, this bit indicates a VC1 TBWRR request was put into the run

behind. This will likely result in a resulting in a contract violation due

to the (G)MCH Express port taking too long to service the isochronous

request.

If this bit is already set, then an interrupt message will not be sent on

a new error event.

RWC/S

(G)MCH Software Generated Event for SMI (GSGESMI):

This indicates the source of the SMI was a Device 2 Software Event.

RWC/S

(G)MCH Thermal Sensor Event for SMI/SCI/SERR (GTSE): This

bit indicates that a (G)MCH Thermal Sensor trip has occurred and an

SMI, SCI or SERR has been generated. The status bit is set only if a

message is sent based on Thermal event enables in Error command,

SMI command and SCI command registers. A trip point can generate

one of SMI, SCI, or SERR interrupts (two or more per event is invalid).

Multiple trip points can generate the same interrupt, if software

chooses this mode, subsequent trips may be lost. If this bit is already

set, then an interrupt message will not be sent on a new thermal

sensor event.

Reserved

RWC/S

LOCK to non-DRAM Memory Flag (LCKF):

1 = (G)MCH has detected a lock operation to memory space that did

not map into DRAM.

Reserved

RWC/S

DRAM Throttle Flag (DTF):

1 = DRAM Throttling condition occurred.

0 = Software has cleared this flag since the most recent throttling

event.

6:0

Reserved

82G33 Datasheet(PDF) 120 Page - Intel Corporation

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