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82G33 Datasheet(PDF) 116 Page - Intel Corporation |
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82G33 Datasheet(HTML) 116 Page - Intel Corporation |
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116 / 437 page ![]() DRAM Controller Registers (D0:F0) 116 Datasheet 5.1.32 GBSM—Graphics Base of Stolen Memory B/D/F/Type: 0/0/0/PCI Address Offset: A4–A7h Default Value: 00000000h Access: RW/L, RO Size: 32 bits This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0, offset B0h, bits 15:4). Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. Bit Access & Default Description 31:20 RW/L 000h Graphics Base of Stolen Memory (GBSM): This register contains bits 31:20 of the base address of stolen DRAM memory. BIOS determines the base of graphics stolen memory by subtracting the graphics stolen memory size (PCI Device 0, offset 52h, bits 6:4) from TOLUD (PCI Device 0, offset B0h, bits 15:04). Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. 19:0 RO 00000h Reserved |
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