82G33 datasheet(117/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

117

5.1.33

BGSM—Base of GTT stolen Memory

B/D/F/Type:

0/0/0/PCI

Address Offset:

A8–ABh

Default Value:

00000000h

Access:

RW/L, RO

Size:

32 bits

This register contains the base address of stolen DRAM memory for the GTT. BIOS

determines the base of GTT stolen memory by subtracting the GTT graphics stolen

memory size (PCI Device 0 offset 52 bits 9:8) from the graphics stolen memory base

(PCI Device 0, offset A4h, bits 31:20).

Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM

Bit

Access &

Default

Description

31:20

RW/L

000h

Graphics Base of Stolen Memory (GBSM): This register contains

bits 31:20 of the base address of stolen DRAM memory. BIOS

determines the base of graphics stolen memory by subtracting the

GTT graphics stolen memory size (PCI Device 0, offset 52h, bits 9:8)

from the graphics stolen memory base (PCI Device 0, offset A4h, bits

31:20).

Note: This register is locked and becomes Read Only when the D_LCK

bit in the SMRAM register is set.

19:0

00000h

Reserved

5.1.34

TSEGMB—TSEG Memory Base

B/D/F/Type:

0/0/0/PCI

Address Offset:

AC–AFh

Default Value:

00000000h

Access:

RW/L, RO

Size:

32 bits

This register contains the base address of TSEG DRAM memory. BIOS determines the

base of TSEG memory by subtracting the TSEG size (PCI Device 0, offset 9Eh, bits

2:1) from graphics GTT stolen base (PCI Device 0, offset A8h, bits 31:20).

Once D_LCK has been set, these bits becomes read only.

Bit

Access &

Default

Description

31:20

RW/L

000h

TESG Memory base (TSEGMB): This register contains bits 31:20 of

the base address of TSEG DRAM memory. BIOS determines the base

of TSEG memory by subtracting the TSEG size (PCI Device 0, offset

9Eh, bits 2:1) from graphics GTT stolen base (PCI Device 0, offset

A8h, bits 31:20).

Once D_LCK has been set, these bits becomes read only.

19:0

00000h

Reserved

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