82G33 datasheet(119/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

119

Bit

Access &

Default

Description

15:4

RW/L

001h

Top of Low Usable DRAM (TOLUD): This register contains bits

31:20 of an address one byte above the maximum DRAM memory

below 4 GB that is usable by the operating system. Address bits 31:20

programmed to 01h implies a minimum memory size of 1 MB.

Configuration software must set this value to the smaller of the

following 2 choices: maximum amount memory in the system minus

ME stolen memory plus one byte or the minimum address allocated

for PCI memory. Address bits 19:0 are assumed to be 0_0000h for

the purposes of address comparison. The Host interface positively

decodes an address towards DRAM if the incoming address is less than

the value programmed in this register.

Note that the Top of Low Usable DRAM is the lowest address above

both Graphics Stolen memory and TSEG. BIOS determines the base of

Graphics Stolen Memory by subtracting the Graphics Stolen Memory

Size from TOLUD and further decrements by TSEG size to determine

base of TSEG. All the Bits in this register are locked in Intel® TXT

mode.

This register must be 64 MB aligned when reclaim is enabled.

3:0

0000b

Reserved

5.1.36

ERRSTS—Error Status

B/D/F/Type:

0/0/0/PCI

Address Offset:

C8–C9h

Default Value:

0000h

Access:

RO, RWC/S

Size:

16 bits

This register is used to report various error conditions via the SERR DMI messaging

mechanism. An SERR DMI message is generated on a zero to one transition of any of

these flags (if enabled by the ERRCMD and PCICMD registers).

These bits are set regardless of whether or not the SERR is enabled and generated.

After the error processing is complete, the error logging mechanism can be unlocked

by clearing the appropriate status bit by software writing a 1 to it.

Bit

Access &

Default

Description

Reserved

RWC/S

Isochronous TBWRR Run Behind FIFO full (ITCV):

If set, this bit indicates a VC1 TBWRR is running behind, resulting in

the slot timer to stop until the request is able to complete.

If this bit is already set, then an interrupt message will not be sent on

a new error event.

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