82G33 datasheet(115/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

115

5.1.31

TOUUD—Top of Upper Usable Dram

B/D/F/Type:

0/0/0/PCI

Address Offset:

A2–A3h

Default Value:

0000h

Access:

RW/L

Size:

16 bits

This 16 bit register defines the Top of Upper Usable DRAM.

Configuration software must set this value to TOM minus all EP stolen memory if

reclaim is disabled. If reclaim is enabled, this value must be set to (reclaim limit + 1

byte) 64 MB aligned since reclaim limit is 64 MB aligned. Address bits 19:0 are

assumed to be 000_0000h for the purposes of address comparison. The Host interface

positively decodes an address towards DRAM if the incoming address is less than the

value programmed in this register and greater than or equal to 4 GB.

These bits are Intel® TXT lockable.

Bit

Access &

Default

Description

15:0

RW/L

0000h

TOUUD (TOUUD): This register contains bits 35 to 20 of an address

one byte above the maximum DRAM memory above 4 G that is usable

by the operating system. Configuration software must set this value to

TOM minus all EP stolen memory if reclaim is disabled. If reclaim is

enabled, this value must be set to (reclaim limit + 1 byte) 64 MB

aligned since reclaim limit is 64 MB aligned. Address bits 19:0 are

assumed to be 000_0000h for the purposes of address comparison.

The Host interface positively decodes an address towards DRAM if the

incoming address is less than the value programmed in this register

and greater than 4 GB.

All the Bits in this register are locked in Intel® TXT mode.

82G33 Datasheet(PDF) 115 Page - Intel Corporation