82G33 datasheet(114/437 Pages) INTEL

114 / 437 page

DRAM Controller Registers (D0:F0)

114

Datasheet

Bit

Access &

Default

Description

RW/L

TSEG Enable (T_EN): Enabling of SMRAM memory for Extended

SMRAM space only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG

is enabled to appear in the appropriate physical address space. Note that

once D_LCK is set, this bit becomes read only.

5.1.30

TOM—Top of Memory

B/D/F/Type:

0/0/0/PCI

Address Offset:

A0–A1h

Default Value:

0001h

Access:

RO, RW/L

Size:

16 bits

This Register contains the size of physical memory. BIOS determines the memory size

reported to the OS using this Register.

Bit

Access &

Default

Description

15:10

00h

Reserved

9:0

RW/L

001h

Top of Memory (TOM): This register reflects the total amount of

populated physical memory. This is NOT necessarily the highest main

memory address (holes may exist in main memory address map due

to addresses allocated for memory mapped I/O). These bits

correspond to address bits 35:26 (64 MB granularity). Bits 25:0 are

assumed to be 0. All the bits in this register are locked in Intel® TXT

mode.

82G33 Datasheet(PDF) 114 Page - Intel Corporation

82G33 Datasheet(HTML) 114 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL