82G33 datasheet(111/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

111

5.1.26

REMAPBASE—Remap Base Address Register

B/D/F/Type:

0/0/0/PCI

Address Offset:

98–99h

Default Value:

03FFh

Access:

RO, RW/L

Size:

16 bits

Bit

Access &

Default

Description

15:10

000000b

Reserved

9:0

RW/L

3FFh

Remap Base Address [35:26] (REMAPBASE): The value in this

window is inclusive of this address. In the decoder A[25:0] of the

Remap Base Address are assumed to be 0s. Thus, the bottom of the

defined memory range will be aligned to a 64 MB boundary.

When the value in this register is greater than the value programmed

into the Remap Limit register, the Remap window is disabled.

These bits are Intel® TXT lockable or ME stolen Memory lockable.

5.1.27

REMAPLIMIT—Remap Limit Address Register

B/D/F/Type:

0/0/0/PCI

Address Offset:

9A–9Bh

Default Value:

0000h

Access:

RO, RW/L

Size:

16 bits

Bit

Access &

Default

Description

15:10

000000b

Reserved

9:0

RW/L

000h

Remap Limit Address [35:26] (REMAPLMT): The value in this

window is inclusive of this address. In the decoder A[25:0] of the

remap limit address are assumed to be Fhs. Thus the top of the defined

range will be one less than a 64 MB boundary.

When the value in this register is less than the value programmed into

the Remap Base register, the Remap window is disabled.

These Bits are Intel® TXT lockable or ME stolen Memory lockable.

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