82G33 datasheet(122/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

122

Datasheet

5.1.38

SMICMD—SMI Command

B/D/F/Type:

0/0/0/PCI

Address Offset:

CC–CDh

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

This register enables various errors to generate an SMI DMI special cycle. When an

error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI

special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,

respectively. Note that one and only one message type can be enabled.

Bit

Access &

Default

Description

15:12

Reserved

SMI on (G)MCH Thermal Sensor Trip (TSTSMI):

1 = A SMI DMI special cycle is generated by (G)MCH when the

thermal sensor trip requires an SMI. A thermal sensor trip point

cannot generate more than one special cycle.

0 = Reporting of this condition via SMI messaging is disabled.

10:0

Reserved

5.1.39

SKPD—Scratchpad Data

B/D/F/Type:

0/0/0/PCI

Address Offset:

DC–DFh

Default Value:

00000000h

Access:

Size:

32 bits

This register holds 32 writable bits with no functionality behind them. It is for the

convenience of BIOS and graphics drivers.

Bit

Access &

Default

Description

31:0

00000000h

Scratchpad Data (SKPD): 1 DWord of data storage.

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