82G33 datasheet(125/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

125

Bit

Access &

Default

Description

82Q35, 82Q33, 82G33 GMCH

Internal Graphics Disable (IGD):

0 = There is a graphics engine within this GMCH. Internal Graphics

Device (Device #2) is enabled and all of its memory and I/O

spaces are accessible. Configuration cycles to Device 2 will be

completed within the GMCH. All non-SMM memory and IO accesses

to VGA will be handled based on Memory and IO enables of Device

2 and IO registers within Device 2 and VGA Enable of the PCI to

PCI bridge control register in Device 1 (If PCI Express GFX attach is

supported). A selected amount of Graphics Memory space is pre-

allocated from the main memory based on Graphics Mode Select

(GMS in the GMCH Control Register). Graphics Memory is pre-

allocated above TSEG Memory.

1 = There is no graphics engine within this GMCH. Internal Graphics

Device (Device #2) and all of its memory and I/O functions are

disabled. Configuration cycle targeted to Device 2 will be passed on

to DMI. In addition, all clocks to internal graphics logic are turned

off. All non-SMM memory and IO accesses to VGA will be handled

based on VGA Enable of the PCI to PCI bridge control register in

Device 1. DEVEN [4:3] (Device 0, offset 54h) have no meaning.

Device 2 Functions 0 and 1 are disabled and hidden.

82P35 MCH

Reserved

PEG Port x16 Disable (PEGX16D):

0 = Capable of x16 PEG Port.

1 = Not Capable of x16 PEG port, instead PEG limited to x8 and below.

Causes PEG port to enable and train logical lanes 7:0 only. Logical

lanes 15:8 are powered down, and the Max Link Width field of the

Link Capability register reports x8 instead of x16. (in the case of

lane reversal, lanes 15:8 are active and lanes 7:0 are powered

down)

PCI Express Port Disable (PEGPD):

0 = There is a PCI Express Port on this GMCH. Device 1 and associated

memory spaces are accessible. All non-SIMM memory and IO

accesses to VGA will be handled based on VGA Enable of the PCI to

PCI bridge control register in Device 1 and VGA settings controlling

internal graphics VGA if internal graphics is enabled.

1 = There is no PCI Express Port on this GMCH. Device 1 and

associated memory and IO spaces are disabled by hardwiring the

D1EN field bit 1 of the Device Enable register (DEVEN Dev 0 Offset

54h). In addition, Next_Pointer = 00h, VGA memory and IO cannot

decode to the PCI Express interface. From a Physical Layer

perspective, all 16 lanes are powered down and the link does not

attempt to train.

43:39

00000b

Reserved

82G33 Datasheet(PDF) 125 Page - Intel Corporation

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