82G33 datasheet(121/437 Pages) INTEL

121 / 437 page

DRAM Controller Registers (D0:F0)

Datasheet

121

5.1.37

ERRCMD—Error Command

B/D/F/Type:

0/0/0/PCI

Address Offset:

CA–CBh

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

This register controls the (G)MCH responses to various system errors. Since the

(G)MCH does not have an SERR# signal, SERR messages are passed from the (G)MCH

to the ICH over DMI.

When a bit in this register is set, a SERR message will be generated on DMI whenever

the corresponding flag is set in the ERRSTS register. The actual generation of the

SERR message is globally enabled for Device #0 via the PCI Command register.

Bit

Access &

Default

Description

15:12

Reserved

SERR on (G)MCH Thermal Sensor Event (TSESERR):

1 = The (G)MCH generates a DMI SERR special cycle when bit 11 of

the ERRSTS is set. The SERR must not be enabled at the same

time as the SMI for the same thermal sensor event.

0 = Reporting of this condition via SERR messaging is disabled.

Reserved

SERR on LOCK to non-DRAM Memory (LCKERR):

1 = The (G)MCH will generate a DMI SERR special cycle whenever a

processor lock cycle is detected that does not hit DRAM.

0 = Reporting of this condition via SERR messaging is disabled.

8:7

00b

Reserved

6:0

Reserved

82G33 Datasheet(PDF) 121 Page - Intel Corporation

82G33 Datasheet(HTML) 121 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL