82G33 datasheet(123/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

123

5.1.40

CAPID0—Capability Identifier

B/D/F/Type:

0/0/0/PCI

Address Offset:

E0–EAh

Default Value:

00000100000000010B0009h

Access:

Size:

88 bits

Control of bits in this register are only required for customer visible SKU

differentiation.

Bit

Access &

Default

Description

87:79

Reserved

82Q35, 82Q33, 82G33 GMCH

Dual Independent Display Disable (DIDD): This bit determines

whether the component is capable of Dual Independent Display

functionality. This functionality requires both functions (0 and 1) to be

visible in the Internal Graphics Device 2. This capability is only

meaningful if the component is capable of Internal Graphics.

Definitions:

• Clone mode – Same Image. Different display timing on each pipe.

• Twin mode – Same Image. Same exact display timings.

Extended Desktop mode – Unique images. Different display timings on

each pipe.

When Device 2 Function 1 is hidden, the second controller and its

associated frame buffer are no longer visible to the Operating System.

The OS thinks our device has only one display controller and stops

supporting Extended Desktop mode.

0 = Capable of Dual Independent Display (independent frame buffers),

Extended Desktop mode is supported.

1 = Not capable of Dual Independent Display. Hardwires bit 4 of the

Device Enable (DEVEN) register (Device 0 Offset 54h) to '0'. Clone

mode and twin mode are still supported (single frame buffer).

82P35 MCH

Reserved

Dual Channel Disable (DCD):

0 = Dual channel operation allowed

1 = Only single channel operation allowed

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