82G33 datasheet(127/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

127

5.2

MCHBAR

The MCHBAR registers are offset from the MCHBAR base address. Table 5-2 provides

an address map of the registers listed by address offset in ascending order. Detailed

Table 5-2. MCHBAR Register Address Map

Address

Offset

Default

Value

Access

111h

CHDECMISC

Channel Decode

Miscellaneous

00h

RW/L

200–01h

C0DRB0

Channel 0 DRAM Rank

Boundary Address 0

0000h

RO,

RW/L

202–203h

C0DRB1

Channel 0 DRAM Rank

Boundary Address 1

0000h

RW/L,

204–205h

C0DRB2

Channel 0 DRAM Rank

Boundary Address 2

0000h

RW/L,

206–207h

C0DRB3

Channel 0 DRAM Rank

Boundary Address 3

0000h

RW/L,

208–209h

C0DRA01

Channel 0 DRAM Rank 0,1

Attribute

0000h

RW/L

20A–20Bh

C0DRA23

Channel 0 DRAM Rank 2,3

Attribute

0000h

RW/L

250–251h

C0CYCTRKPCHG

Channel 0 CYCTRK PCHG

0000h

RW, RO

252–255h

C0CYCTRKACT

Channel 0 CYCTRK ACT

00000000h

RW, RO

256–257h

C0CYCTRKWR

Channel 0 CYCTRK WR

0000h

258–25Ah

C0CYCTRKRD

Channel 0 CYCTRK READ

000000h

RW, RO

25B–25Ch

C0CYCTRKREFR

Channel 0 CYCTRK REFR

0000h

RO, RW

260–263h

C0CKECTRL

Channel 0 CKE Control

00000800h

RO, RW,

RW/L

269–26Eh

C0REFRCTRL

Channel 0 DRAM Refresh

Control

021830000

C30h

RW, RO

29C–29Fh

C0ODTCTRL

Channel 0 ODT Control

00000000h

RO, RW

600–601h

C1DRB0

Channel 1 DRAM Rank

Boundary Address 0

0000h

RW/L,

602–603h

C1DRB1

Channel 1 DRAM Rank

Boundary Address 1

0000h

RW/L,

604–605h

C1DRB2

Channel 1 DRAM Rank

Boundary Address 2

0000h

RW/L,

606–607h

C1DRB3

Channel 1 DRAM Rank

Boundary Address 3

0000h

RW/L,

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