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PCI Express* Registers (D1:F0)

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Datasheet

PCI Express* Registers (D1:F0)

Device 1 (D1), Funciton 0 (F0) contains the controls associated with the PCI Express

x16 root port that is the intended to attach as the point for external graphics. It also

functions as the virtual PCI-to-PCI bridge.

Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a

valid value unless the register value is stable.

The PCI Express* Specification defines two types of reserved bits.

Reserved and Preserved:

1. Reserved for future RW implementations; software must preserve value read

for writes to bits.

2. Reserved and Zero: Reserved for future R/WC/S implementations; software

must use 0 for writes to bits.

Unless explicitly documented as Reserved and Zero, all bits marked as reserved are

part of the Reserved and Preserved type, which have historically been the typical

definition for Reserved.

Note: Most (if not all) control bits in this device cannot be modified unless the link is down.

Software is required to first Disable the link, then program the registers, and then re-

enable the link (which will cause a full-retrain with the new settings).

Table 6-1. PCI Express* Register Address Map (D1:F0)

Address

Offset

Symbol

Default

Value

Access

00–01h

VID1

Vendor Identification

8086h

02–03h

DID1

Device Identification

29C1h

04–05h

PCICMD1

PCI Command

0000h

RO, RW

06–07h

PCISTS1

PCI Status

0010h

RO, RWC

08h

RID1

Revision Identification

00h

09–0Bh

CC1

Class Code

060400h

0Ch

CL1

Cache Line Size

00h

0Eh

HDR1

Header Type

01h

18h

PBUSN1

Primary Bus Number

00h

19h

SBUSN1

Secondary Bus Number

00h

1Ah

SUBUSN1

Subordinate Bus Number

00h

1Ch

IOBASE1

I/O Base Address

F0h

RW, RO

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