Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

82G33 Datasheet(PDF) 177 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 177 Page - Intel Corporation

Back Button 82G33 Datasheet HTML 173Page - Intel Corporation 82G33 Datasheet HTML 174Page - Intel Corporation 82G33 Datasheet HTML 175Page - Intel Corporation 82G33 Datasheet HTML 176Page - Intel Corporation 82G33 Datasheet HTML 177Page - Intel Corporation 82G33 Datasheet HTML 178Page - Intel Corporation 82G33 Datasheet HTML 179Page - Intel Corporation 82G33 Datasheet HTML 180Page - Intel Corporation 82G33 Datasheet HTML 181Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 177 / 437 page
background image
DRAM Controller Registers (D0:F0)
Datasheet
177
5.3.2
EPLE1D—EP Link Entry 1 Description
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset:
50–53h
Default Value:
01000000h
Access:
RO, RWO
Size:
32 bits
This register provides the first part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
01h
Target Port Number (TPN): Specifies the port number associated
with the element targeted by this link entry (DMI). The target port
number is with respect to the component that contains this element as
specified by the target component ID.
23:16
RWO
00h
Target Component ID (TCID): This field indicates the physical or
logical component that is targeted by this link entry.
BIOS Requirement: Must be initialized according to guidelines in the
PCI Express* Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
15:2
RO
0000h
Reserved
1
RO
0b
Link Type (LTYP): This field indicates that the link points to memory-
mapped space (for RCRB). The link address specifies the 64-bit base
address of the target RCRB.
0
RWO
0b
Link Valid (LV):
0 = Link Entry is not valid and will be ignored.
1 = Link Entry specifies a valid link.
5.3.3
EPLE1A—EP Link Entry 1 Address
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset:
58–5Fh
Default Value:
0000000000000000h
Access:
RO, RWO
Size:
64 bits
This register provides the second part of a Link Entry which declares an internal link to
another Root Complex Element.
Bit
Access &
Default
Description
63:36
RO
0s
Reserved
35:12
RWO
0s
Link Address (LA): This field contains the memory mapped base
address of the RCRB that is the target element (DMI) for this link
entry.
11:0
RO
0s
Reserved



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com