Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

82G33 Datasheet(PDF) 176 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 176 Page - Intel Corporation

Back Button 82G33 Datasheet HTML 172Page - Intel Corporation 82G33 Datasheet HTML 173Page - Intel Corporation 82G33 Datasheet HTML 174Page - Intel Corporation 82G33 Datasheet HTML 175Page - Intel Corporation 82G33 Datasheet HTML 176Page - Intel Corporation 82G33 Datasheet HTML 177Page - Intel Corporation 82G33 Datasheet HTML 178Page - Intel Corporation 82G33 Datasheet HTML 179Page - Intel Corporation 82G33 Datasheet HTML 180Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 176 / 437 page
background image
DRAM Controller Registers (D0:F0)
176
Datasheet
5.3
EPBAR
Table 5-4. EPBAR Register Address Map
Address
Offset
Symbol
Register Name
Default
Value
Access
44–47h
EPESD
EP Element Self Description
00000201h
RO, RWO
50–53h
EPLE1D
EP Link Entry 1 Description
01000000h
RO, RWO
58–5Fh
EPLE1A
EP Link Entry 1 Address
0000000000
000000h
RO, RWO
60–63h
EPLE2D
EP Link Entry 2 Description
02000002h
RO, RWO
68–6Fh
EPLE2A
EP Link Entry 2 Address
0000000000
008000h
RO
5.3.1
EPESD—EP Element Self Description
B/D/F/Type:
0/0/0/PXPEPBAR
Address Offset:
44–47h
Default Value:
00000201h
Access:
RO, RWO
Size:
32 bits
This register provides information about the root complex element containing this Link
Declaration Capability.
Bit
Access &
Default
Description
31:24
RO
00h
Port Number (PN): This field specifies the port number associated
with this element with respect to the component that contains this
element. A value of 00h indicates to configuration software that this is
the default Express port.
23:16
RWO
00h
Component ID (CID): This field indicates identifies the physical
component that contains this Root Complex Element.
BIOS Requirement: Must be initialized according to guidelines in the
PCI Express* Isochronous/Virtual Channel Support Hardware
Programming Specification (HPS).
15:8
RO
0sh
Number of Link Entries (NLE): This field indicates the number of
link entries following the Element Self Description. This field reports 2
(one each for PEG and DMI).
7:4
RO
0h
Reserved
3:0
RO
1h
Element Type (ET): This field indicates the type of the Root
Complex Element. Value of 1 h represents a port to system memory.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com