82G33 datasheet(172/437 Pages) INTEL

172 / 437 page

DRAM Controller Registers (D0:F0)

172

Datasheet

5.2.48

TIS—Thermal Interrupt Status

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

CEA–CEBh

Default Value:

0000h

Access:

RO, RWC

Size:

16 bits

This register is used to report which specific error condition resulted in the dev. 0 fn. 0

ERRSTS[Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR Thermal

Event. Software can examine the current state of the thermal zones by examining the

TSS. Software can distinguish internal or external Trip Event by examining EXTTSCS.

Software must write a 1 to clear the status bits in this register.

Following scenario is possible. An interrupt is initiated on a rising temperature trip, the

appropriate DMI cycles are generated, and eventually the software services the

interrupt and sees a rising temperature trip as the cause in the status bits for the

interrupts. Assume that the software then goes and clears the local interrupt status bit

in the TIS register for that trip event. It is possible at this point that a falling

temperature trip event occurs before the software has had the time to clear the global

interrupts status bit. But since software has already looked at the status register

before this event happened, software may not clear the local status flag for this event.

Therefore, after the global interrupt is cleared by software, software must look at the

instantaneous status in the TSS register.

All bits in this register are reset to their defaults by PLTRST#.

Bit

Access &

Default

Description

15:10

00h

Reserved

RWC

Was Catastrophic Thermal Sensor Interrupt Event (WCTSIE):

1 = Indicates that a Catastrophic Thermal Sensor trip based on a

higher to lower temperature transition thru the trip point

0 = No trip for this event

RWC

Was Hot Thermal Sensor Interrupt Event (WHTSIE):

1 = Indicates that a Hot Thermal Sensor trip based on a higher to

lower temperature transition thru the trip point

0 = No trip for this event

RWC

Was Aux0 Thermal Sensor Interrupt Event (WA0TSIE):

1 = Indicates that an Aux0 Thermal Sensor trip based on a higher to

lower temperature transition thru the trip point

0 = No trip for this event Software must write a 1 to clear this status

bit.

6:5

00b

Reserved

82G33 Datasheet(PDF) 172 Page - Intel Corporation

82G33 Datasheet(HTML) 172 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL