82G33 datasheet(174/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

174

Datasheet

5.2.49

TSMICMD—Thermal SMI Command

B/D/F/Type:

0/0/0/MCHBAR

Address Offset:

CF1h

Default Value:

00h

Access:

RO, RW

Size:

8 bits

This register selects specific errors to generate a SMI DMI special cycle, as enabled by

the Device 0 SMI Error Command Register [SMI on (G)MCH Thermal Sensor Trip]. The

SMI must not be enabled at the same time as the SERR/SCI for the thermal sensor

event.

All bits in this register are reset to their defaults by PLTRST#.

Bit

Access &

Default

Description

7:3

00h

Reserved

SMI on (G)MCH Catastrophic Thermal Sensor Trip (SMGCTST):

1 = Does not mask the generation of an SMI DMI special cycle on a

catastrophic thermal sensor trip.

0 = Disable reporting of this condition via SMI messaging.

SMI on (G)MCH Hot Thermal Sensor Trip (SMGHTST):

1 = Does not mask the generation of an SMI DMI special cycle on a

Hot thermal sensor trip.

0 = Disable reporting of this condition via SMI messaging.

SMI on (G)MCH Aux Thermal Sensor Trip (SMGATST):

1 = Does not mask the generation of an SMI DMI special cycle on an

Auxiliary thermal sensor trip.

0 = Disable reporting of this condition via SMI messaging.

82G33 Datasheet(PDF) 174 Page - Intel Corporation