82G33 datasheet(178/437 Pages) INTEL

178 / 437 page

DRAM Controller Registers (D0:F0)

178

Datasheet

5.3.4

EPLE2D—EP Link Entry 2 Description

B/D/F/Type:

0/0/0/PXPEPBAR

Address Offset:

60–63h

Default Value:

02000002h

Access:

RO, RWO

Size:

32 bits

This register provides the first part of a Link Entry which declares an internal link to

another Root Complex Element.

Bit

Access &

Default

Description

31:24

02h

Target Port Number (TPN): This field specifies the port number

associated with the element targeted by this link entry (PEG). The

target port number is with respect to the component that contains

this element as specified by the target component ID.

23:16

RWO

00h

Target Component ID (TCID): This field indicates the physical or

logical component that is targeted by this link entry. A value of 0 is

reserved. Component IDs start at 1. This value is a mirror of the

value in the Component ID field of all elements in this component.

BIOS Requirement: Must be initialized according to guidelines in the

PCI Express* Isochronous/Virtual Channel Support Hardware

Programming Specification (HPS).

15:2

Reserved

Link Type (LTYP): This field indicates that the link points to

configuration space of the integrated device which controls the x16

root port.

The link address specifies the configuration address (segment, bus,

device, function) of the target root port.

RWO

Link Valid (LV):

0 = Link Entry is not valid and will be ignored.

1 = Link Entry specifies a valid link.

82G33 Datasheet(PDF) 178 Page - Intel Corporation

82G33 Datasheet(HTML) 178 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL