82G33 datasheet(184/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

184

Datasheet

6.1.3

PCICMD1—PCI Command

B/D/F/Type:

0/1/0/PCI

Address Offset:

04–05h

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

Bit

Access &

Default

Description

15:11

00h

Reserved

INTA Assertion Disable (INTAAD): This bit 0nly affects interrupts

generated by the device (PCI INTA from a PME or Hot Plug event)

controlled by this command register. It does not affect upstream MSIs,

upstream PCI INTA–INTD assert and de-assert messages.

0 = This device is permitted to generate INTA interrupt messages.

1 = This device is prevented from generating interrupt messages. Any

INTA emulation interrupts already asserted must be de-asserted

when this bit is set.

Fast Back-to-Back Enable (FB2B): Not Applicable or Implemented.

Hardwired to 0.

SERR# Message Enable (SERRE1): Controls Device 1 SERR#

messaging. The (G)MCH communicates the SERR# condition by

sending an SERR message to the ICH. This bit, when set, enables

reporting of non-fatal and fatal errors detected by the device to the

Root Complex. Note that errors are reported if enabled either through

this bit or through the PCI Express specific bits in the Device Control

0 = The SERR message is generated by the (G)MCH for Device #1 only

under conditions enabled individually through the Device Control

1 = The (G)MCH is enabled to generate SERR messages which will be

sent to the ICH for specific Device #1 error conditions

generated/detected on the primary side of the virtual PCI to PCI

bridge (not those received by the secondary side). The status of

SERRs generated is reported in the PCISTS1 register.

Reserved: Not Applicable or Implemented. Hardwired to 0.

Parity Error Response Enable (PERRE): This bit controls whether or

not the Master Data Parity Error bit in the PCI Status register can bet

set.

0 = Master Data Parity Error bit in PCI Status register can NOT be set.

1 = Master Data Parity Error bit in PCI Status register CAN be set.

VGA Palette Snoop (VGAPS): Not Applicable or Implemented.

Hardwired to 0.

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