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82G33 Datasheet(PDF) 187 Page - Intel Corporation |
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82G33 Datasheet(HTML) 187 Page - Intel Corporation |
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187 / 437 page  PCI Express* Registers (D1:F0) Datasheet 187 Bit Access & Default Description 4 RO 1b Capabilities List (CAPL): Indicates that a capabilities list is present. Hardwired to 1. 3 RO 0b INTA Status (INTAS): Indicates that an interrupt message is pending internally to the device. Only PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert and de-assert messages). The INTA Assertion Disable bit, PCICMD1[10], has no effect on this bit. 2:0 RO 000b Reserved 6.1.5 RID1—Revision Identification B/D/F/Type: 0/1/0/PCI Address Offset: 08h Default Value: 00h Access: RO Size: 8 bits This register contains the revision number of the (G)MCH device 1. These bits are read only and writes to this register have no effect. Bit Access & Default Description 7:0 RO 00h Revision Identification Number (RID1): This is an 8-bit value that indicates the revision identification number for the (G)MCH Device 0. Refer to the Intel® 3 Series Express Chipset Family Specification Update for the value of the Revision ID register. 6.1.6 CC1—Class Code B/D/F/Type: 0/1/0/PCI Address Offset: 09–0Bh Default Value: 060400h Access: RO Size: 24 bits This register identifies the basic function of the device, a more specific sub-class, and a register- specific programming interface. Bit Access & Default Description 23:16 RO 06h Base Class Code (BCC): This field indicates the base class code for this device. This code has the value 06h, indicating a Bridge device. 15:8 RO 04h Sub-Class Code (SUBCC): This field indicates the sub-class code for this device. The code is 04h indicating a PCI to PCI Bridge. 7:0 RO 00h Programming Interface (PI): This field indicates the programming interface of this device. This value does not specify a particular register set layout and provides no practical use for this device. |
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