82G33 datasheet(190/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

190

Datasheet

6.1.12

IOBASE1—I/O Base Address

B/D/F/Type:

0/1/0/PCI

Address Offset:

1Ch

Default Value:

F0h

Access:

RW, RO

Size:

8 bits

This register controls the processor to PCI Express-G I/O access routing based on the

following formula:

IO_BASE ≤ address ≤ IO_LIMIT

Only the upper 4 bits are programmable. For the purpose of address decode, address

bits A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will

be aligned to a 4 KB boundary.

Bit

Access &

Default

Description

7:4

I/O Address Base (IOBASE): This field corresponds to A[15:12] of

the I/O addresses passed by bridge 1 to PCI Express.

3:0

Reserved

6.1.13

IOLIMIT1—I/O Limit Address

B/D/F/Type:

0/1/0/PCI

Address Offset:

1Dh

Default Value:

00h

Access:

RW, RO

Size:

8 bits

This register controls the processor to PCI Express-G I/O access routing based on the

following formula:

IO_BASE ≤ address ≤ IO_LIMIT

Only the upper 4 bits are programmable. For the purpose of address decode, address

bits A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range

will be at the top of a 4 KB aligned address block.

Bit

Access &

Default

Description

7:4

I/O Address Limit (IOLIMIT): This field corresponds to A[15:12] of

the I/O address limit of device 1. Devices between this upper limit and

IOBASE1 will be passed to the PCI Express hierarchy associated with

this device.

3:0

Reserved

82G33 Datasheet(PDF) 190 Page - Intel Corporation

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