82G33 datasheet(189/437 Pages) INTEL

189 / 437 page

PCI Express* Registers (D1:F0)

Datasheet

189

6.1.10

SBUSN1—Secondary Bus Number

B/D/F/Type:

0/1/0/PCI

Address Offset:

19h

Default Value:

00h

Access:

Size:

8 bits

This register identifies the bus number assigned to the second bus side of the "virtual"

bridge (i.e., to PCI Express-G). This number is programmed by the PCI configuration

software to allow mapping of configuration cycles to PCI Express-G.

Bit

Access &

Default

Description

7:0

00h

Secondary Bus Number (BUSN): This field is programmed by

configuration software with the bus number assigned to PCI Express.

6.1.11

SUBUSN1—Subordinate Bus Number

B/D/F/Type:

0/1/0/PCI

Address Offset:

1Ah

Default Value:

00h

Access:

Size:

8 bits

This register identifies the subordinate bus (if any) that resides at the level below PCI

Express-G. This number is programmed by the PCI configuration software to allow

mapping of configuration cycles to PCI Express-G.

Bit

Access &

Default

Description

7:0

00h

Subordinate Bus Number (BUSN): This register is programmed by

configuration software with the number of the highest subordinate bus

that lies behind the device #1 bridge. When only a single PCI device

resides on the PCI Express segment, this register will contain the same

value as the SBUSN1 register.

82G33 Datasheet(PDF) 189 Page - Intel Corporation

82G33 Datasheet(HTML) 189 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL