82G33 datasheet(191/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

Datasheet

191

6.1.14

SSTS1—Secondary Status

B/D/F/Type:

0/1/0/PCI

Address Offset:

1E–1Fh

Default Value:

0000h

Access:

RWC, RO

Size:

16 bits

SSTS1 is a 16-bit status register that reports the occurrence of error conditions

associated with secondary side (i.e., PCI Express side) of the "virtual" PCI-PCI bridge

embedded within (G)MCH.

Bit

Access &

Default

Description

RWC

Detected Parity Error (DPE): This bit is set by the Secondary Side

for a Type 1 Configuration Space header device whenever it receives a

Poisoned TLP, regardless of the state of the Parity Error Response

Enable bit in the Bridge Control Register.

RWC

Received System Error (RSE): This bit is set when the Secondary

Side for a Type 1 configuration space header device receives an

ERR_FATAL or ERR_NONFATAL.

RWC

Received Master Abort (RMA): This bit is set when the Secondary

Side for Type 1 Configuration Space Header Device (for requests

initiated by the Type 1 Header Device itself) receives a Completion

with Unsupported Request Completion Status.

RWC

Received Target Abort (RTA): This bit is set when the Secondary

Side for Type 1 Configuration Space Header Device (for requests

initiated by the Type 1 Header Device itself) receives a Completion

with Completer Abort Completion Status.

Signaled Target Abort (STA): Not Applicable or Implemented.

Hardwired to 0. The (G)MCH does not generate Target Aborts (the

(G)MCH will never complete a request using the Completer Abort

Completion status).

10:9

00b

DEVSELB Timing (DEVT): Not Applicable or Implemented.

Hardwired to 0.

RWC

Master Data Parity Error (SMDPE): When set, this bit indicates that

the (G)MCH received across the link (upstream) a Read Data

Completion Poisoned TLP (EP=1). This bit can only be set when the

Parity Error Enable bit in the Bridge Control register is set.

Fast Back-to-Back (FB2B): Not Applicable or Implemented.

Hardwired to 0.

Reserved

66/60 MHz capability (CAP66): Not Applicable or Implemented.

Hardwired to 0.

4:0

00h

Reserved

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