82G33 datasheet(194/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

194

Datasheet

6.1.17

PMBASE1—Prefetchable Memory Base Address

B/D/F/Type:

0/1/0/PCI

Address Offset:

24–25h

Default Value:

FFF1h

Access:

RW, RO

Size:

16 bits

This register in conjunction with the corresponding Upper Base Address register

controls the processor-to-PCI Express prefetchable memory access routing based on

the following formula:

PREFETCHABLE_MEMORY_BASE ≤ address ≤

PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits

A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register

are read/write and correspond to address bits A[39:32] of the 40-bit address. This

decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined

memory address range will be aligned to a 1 MB boundary.

Bit

Access &

Default

Description

15:4

FFFh

Prefetchable Memory Base Address (MBASE): This field

corresponds to A[31:20] of the lower limit of the memory range that

will be passed to PCI Express.

3:0

64-bit Address Support: This field indicates that the upper 32 bits of

the prefetchable memory region base address are contained in the

Prefetchable Memory base Upper Address register at 28h.

82G33 Datasheet(PDF) 194 Page - Intel Corporation