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82G33 Datasheet(PDF) 198 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 198 Page - Intel Corporation

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PCI Express* Registers (D1:F0)
198
Datasheet
6.1.21
CAPPTR1—Capabilities Pointer
B/D/F/Type:
0/1/0/PCI
Address Offset:
34h
Default Value:
88h
Access:
RO
Size:
8 bits
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
Bit
Access &
Default
Description
7:0
RO
88h
First Capability (CAPPTR1): The first capability in the list is the
Subsystem ID and Subsystem Vendor ID Capability.
6.1.22
INTRLINE1—Interrupt Line
B/D/F/Type:
0/1/0/PCI
Address Offset:
3Ch
Default Value:
00h
Access:
RW
Size:
8 bits
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Bit
Access &
Default
Description
7:0
RW
00h
Interrupt Connection (INTCON): Used to communicate interrupt line
routing information.
6.1.23
INTRPIN1—Interrupt Pin
B/D/F/Type:
0/1/0/PCI
Address Offset:
3Dh
Default Value:
01h
Access:
RO
Size:
8 bits
This register specifies which interrupt pin this device uses.
Bit
Access &
Default
Description
7:0
RO
01h
Interrupt Pin (INTPIN): As a single function device, the PCI Express
device specifies INTA as its interrupt pin. 01h=INTA.



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