82G33 datasheet(199/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

Datasheet

199

6.1.24

BCTRL1—Bridge Control

B/D/F/Type:

0/1/0/PCI

Address Offset:

3E–3Fh

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

This register provides extensions to the PCICMD1 register that are specific to PCI-to-

PCI bridges. The BCTRL provides additional control for the secondary interface (i.e.,

PCI Express) as well as some bits that affect the overall behavior of the "virtual" Host-

PCI Express bridge in the (G)MCH (e.g., VGA compatible address ranges mapping).

Bit

Access &

Default

Description

15:12

Reserved

Discard Timer SERR# Enable (DTSERRE): Not Applicable or

Implemented. Hardwired to 0.

Discard Timer Status (DTSTS): Not Applicable or Implemented.

Hardwired to 0.

Secondary Discard Timer (SDT): Not Applicable or Implemented.

Hardwired to 0.

Primary Discard Timer (PDT): Not Applicable or Implemented.

Hardwired to 0.

Fast Back-to-Back Enable (FB2BEN): Not Applicable or

Implemented. Hardwired to 0.

Secondary Bus Reset (SRESET): Setting this bit triggers a hot reset

on the corresponding PCI Express Port. This will force the LTSSM to

transition to the Hot Reset state (via Recovery) from L0, L0s, or L1

states.

Master Abort Mode (MAMODE): Does not apply to PCI Express.

Hardwired to 0.

VGA 16-bit Decode (VGA16D): Enables the PCI-to-PCI bridge to

provide 16-bit decoding of VGA I/O address precluding the decoding of

alias addresses every 1 KB. This bit only has meaning if bit 3 (VGA

Enable) of this register is also set to 1, enabling VGA I/O decoding and

forwarding by the bridge.

0 = Execute 10-bit address decodes on VGA I/O accesses.

1 = Execute 16-bit address decodes on VGA I/O accesses.

VGA Enable (VGAEN): This bit controls the routing of processor

initiated transactions targeting VGA compatible I/O and memory

address ranges.

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