82G33 datasheet(197/437 Pages) INTEL

197 / 437 page

PCI Express* Registers (D1:F0)

Datasheet

197

6.1.20

PMLIMITU1—Prefetchable Memory Limit Address

B/D/F/Type:

0/1/0/PCI

Address Offset:

2C–2Fh

Default Value:

00000000h

Access:

Size:

32 bits

The functionality associated with this register is present in the PEG design

implementation.

This register in conjunction with the corresponding Upper Limit Address register

controls the processor-to-PCI Express prefetchable memory access routing based on

the following formula:

PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits

A[31:20] of the 40- bit address. The lower 8 bits of the Upper Limit Address register

are read/write and correspond to address bits A[39:32] of the 40-bit address. This

decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined

memory address range will be at the top of a 1MB aligned memory block.

Note that prefetchable memory range is supported to allow segregation by the

configuration software between the memory ranges that must be defined as UC and

the ones that can be designated as a USWC (i.e. prefetchable) from the processor

perspective.

Bit

Access &

Default

Description

31:0

00000000h

Prefetchable Memory Address Limit (MLIMITU): This field

corresponds to A[63:32] of the upper limit of the prefetchable

Memory range that will be passed to PCI Express.

82G33 Datasheet(PDF) 197 Page - Intel Corporation