82G33 datasheet(202/437 Pages) INTEL

202 / 437 page

PCI Express* Registers (D1:F0)

202

Datasheet

6.1.26

PM_CS1—Power Management Control/Status

B/D/F/Type:

0/1/0/PCI

Address Offset:

84–87h

Default Value:

00000000h

Access:

RO, RW/S, RW

Size:

32 bits

Bit

Access &

Default

Description

31:16

0000h

Reserved: Not Applicable or Implemented. Hardwired to 0.

PME Status (PMESTS): Indicates that this device does not support

PME# generation from D3cold.

14:13

00b

Data Scale (DSCALE): Indicates that this device does not support

the power management data register.

12:9

Data Select (DSEL): Indicates that this device does not support the

power management data register.

RW/S

PME Enable (PMEE): Indicates that this device does not generate

PMEB assertion from any D-state.

0 = PMEB generation not possible from any D State

1 = PMEB generation enabled from any D State

The setting of this bit has no effect on hardware.

See PM_CAP[15:11]

7:2

00h

Reserved

1:0

00b

Power State (PS): This field indicates the current power state of this

device and can be used to set the device into a new power state. If

software attempts to write an unsupported state to this field, write

operation must complete normally on the bus, but the data is

discarded and no state change occurs.

00 = D0

01 = D1 (Not supported in this device.

10 = D2 (Not supported in this device.)

11 = D3

Support of D3cold does not require any special action.

While in the D3hot state, this device can only act as the target of PCI

configuration transactions (for power management control). This

device also cannot generate interrupts or respond to MMR cycles in the

D3 state. The device must return to the D0 state to be fully-functional.

When the Power State is other than D0, the bridge will Master Abort

(i.e., not claim) any downstream cycles (with exception of type 0

configuration cycles). Consequently, these unclaimed cycles will go

down DMI and come back up as Unsupported Requests, which the

(G)MCH logs as Master Aborts in Device 0 PCISTS[13]

There is no additional hardware functionality required to support these

Power States.

82G33 Datasheet(PDF) 202 Page - Intel Corporation

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