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82G33 Datasheet(PDF) 206 Page - Intel Corporation |
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82G33 Datasheet(HTML) 206 Page - Intel Corporation |
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206 / 437 page ![]() PCI Express* Registers (D1:F0) 206 Datasheet 6.1.33 PEG_CAPL—PCI Express*-G Capability List B/D/F/Type: 0/1/0/PCI Address Offset: A0–A1h Default Value: 0010h Access: RO Size: 16 bits This register enumerates the PCI Express capability structure. Bit Access & Default Description 15:8 RO 00h Pointer to Next Capability (PNC): This value terminates the capabilities list. The Virtual Channel capability and any other PCI Express specific capabilities that are reported via this mechanism are in a separate capabilities list located entirely within PCI Express Extended Configuration Space. 7:0 RO 10h Capability ID (CID): Identifies this linked list item (capability structure) as being for PCI Express registers. 6.1.34 PEG_CAP—PCI Express*-G Capabilities B/D/F/Type: 0/1/0/PCI Address Offset: A2–A3h Default Value: 0141h Access: RO, RWO Size: 16 bits This register indicates PCI Express device capabilities. Bit Access & Default Description 15:14 RO 00b Reserved 13:9 RO 00h Interrupt Message Number (IMN): Not Applicable or Implemented. Hardwired to 0. 8 RWO 1b Slot Implemented (SI): 0 = The PCI Express Link associated with this port is connected to an integrated component or is disabled. 1 = The PCI Express Link associated with this port is connected to a slot. 7:4 RO 4h Device/Port Type (DPT): Hardwired to 4h to indicate root port of PCI Express Root Complex. 3:0 RO 1h PCI Express Capability Version (PCI EXPRESS*CV): Hardwired to 1 as it is the first version. |
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