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82G33 Datasheet(PDF) 207 Page - Intel Corporation |
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82G33 Datasheet(HTML) 207 Page - Intel Corporation |
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207 / 437 page  PCI Express* Registers (D1:F0) Datasheet 207 6.1.35 DCAP—Device Capabilities B/D/F/Type: 0/1/0/PCI Address Offset: A4–A7h Default Value: 00008000h Access: RO Size: 32 bits This register indicates PCI Express device capabilities. Bit Access & Default Description 31:16 RO 0000h Reserved: Not Applicable or Implemented. Hardwired to 0. 15 RO 1b Role Based Error Reporting (RBER): This bit indicates that this device implements the functionality defined in the Error Reporting ECN as required by the PCI Express 1.1 specification. 14:6 RO 000h Reserved: Not Applicable or Implemented. Hardwired to 0. 5 RO 0b Extended Tag Field Supported (ETFS): Hardwired to indicate support for 5-bit Tags as a Requestor. 4:3 RO 00b Phantom Functions Supported (PFS): Not Applicable or Implemented. Hardwired to 0. 2:0 RO 000b Max Payload Size (MPS): Hardwired to indicate 128B max supported payload for Transaction Layer Packets (TLP). |
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