82G33 datasheet(210/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

210

Datasheet

Bit

Access &

Default

Description

RWC

Correctable Error Detected (CED):

0 = Correctable error Not detected.

1 = Correctable error(s) were detected. Errors are logged in this

the Device Control register.

When Advanced Error Handling is enabled, errors are logged in this

6.1.38

LCAP—Link Capabilities

B/D/F/Type:

0/1/0/PCI

Address Offset:

AC–AFh

Default Value:

02014D01h

Access:

RO, RWO

Size:

32 bits

This register indicates PCI Express device specific capabilities.

Bit

Access &

Default

Description

31:24

02h

Port Number (PN): This field indicates the PCI Express port number

for the given PCI Express link. Matches the value in Element Self

Description[31:24].

23:21

000b

Reserved

Data Link Layer Link Active Reporting Capable (DLLLARC): For a

Downstream Port, this bit must be set to 1b if the component supports

the optional capability of reporting the DL_Active state of the Data

Link Control and Management State Machine. For a hot-plug capable

Downstream Port (as indicated by the Hot-Plug Capable field of the

Slot Capabilities register), this bit must be set to 1b.

For Upstream Ports and components that do not support this optional

capability, this bit must be hardwired to 0b.

Surprise Down Error Reporting Capable (SDERC): For a

Downstream Port, this bit must be set to 1b if the component supports

the optional capability of detecting and reporting a Surprise Down

error condition.

For Upstream Ports and components that do not support this optional

capability, this bit must be hardwired to 0b.

82G33 Datasheet(PDF) 210 Page - Intel Corporation

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