 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
82G33 Datasheet(PDF) 213 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
82G33 Datasheet(HTML) 213 Page - Intel Corporation |
|
|
213 / 437 page  PCI Express* Registers (D1:F0) Datasheet 213 Bit Access & Default Description 4 RW 0b Link Disable (LD): Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state. 0 = Normal operation 1 = Link is disabled. Forces the LTSSM to transition to the Disabled state (via Recovery) from L0, L0s, or L1 states. Link retraining happens automatically on 0 to 1 transition, just like when coming out of reset. 3 RO 0b Read Completion Boundary (RCB): Hardwired to 0 to indicate 64 byte. 2 RW 0b Far-End Digital Loopback (FEDLB): 1:0 RW 00b Active State PM (ASPM): This field controls the level of active state power management supported on the given link. 00 = Disabled 01 = L0s Entry Supported 10 = Reserved 11 = L0s and L1 Entry Supported |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
