82G33 datasheet(208/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

208

Datasheet

6.1.36

DCTL—Device Control

B/D/F/Type:

0/1/0/PCI

Address Offset:

A8–A9h

Default Value:

0000h

Access:

RO, RW

Size:

16 bits

This register provides control for PCI Express device specific capabilities.

The error reporting enable bits are in reference to errors detected by this device, not

error messages received across the link. The reporting of error messages (ERR_CORR,

ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root

Port Command Register.

Bit

Access &

Default

Description

15:8

000h

Reserved

7:5

000b

Max Payload Size (MPS):

000 = 128B max supported payload for Transaction Layer Packets

(TLP). As a receiver, the Device must handle TLPs as large as

the set value; as transmitter, the Device must not generate

TLPs exceeding the set value.

All other encodings are reserved.

Hardware will actually ignore this field. It is writeable only to support

compliance testing.

Reserved: For Enable Relaxed Ordering

Unsupported Request Reporting Enable (URRE): When set,

allows signaling ERR_NONFATAL, ERR_FATAL, or ERR_CORR to the

Root Control register when detecting an unmasked Unsupported

Request (UR). An ERR_CORR is signaled when an unmasked Advisory

Non-Fatal UR is received. An ERR_FATAL or ERR_NONFATAL is sent to

the Root Control register when an uncorrectable non-Advisory UR is

received with the severity bit set in the Uncorrectable Error Severity

Fatal Error Reporting Enable (FERE): When set, enables signaling

of ERR_FATAL to the Root Control register due to internally detected

errors or error messages received across the link. Other bits also

control the full scope of related error reporting.

Non-Fatal Error Reporting Enable (NERE): When set, enables

signaling of ERR_NONFATAL to the Root Control register due to

internally detected errors or error messages received across the link.

Other bits also control the full scope of related error reporting.

Correctable Error Reporting Enable (CERE): When set, enables

signaling of ERR_CORR to the Root Control register due to internally

detected errors or error messages received across the link. Other bits

also control the full scope of related error reporting.

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