82G33 datasheet(204/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

204

Datasheet

6.1.29

MSI_CAPID—Message Signaled Interrupts Capability ID

B/D/F/Type:

0/1/0/PCI

Address Offset:

90–91h

Default Value:

A005h

Access:

Size:

16 bits

When a device supports MSI it can generate an interrupt request to the processor by

writing a predefined data item (a message) to a predefined memory address.

Bit

Access &

Default

Description

15:8

A0h

Pointer to Next Capability (PNC): This contains a pointer to the

next item in the capabilities list which is the PCI Express capability.

7:0

05h

Capability ID (CID): Value of 05h identifies this linked list item

(capability structure) as being for MSI registers.

6.1.30

MC—Message Control

B/D/F/Type:

0/1/0/PCI

Address Offset:

92–93h

Default Value:

0000h

Access:

RW, RO

Size:

16 bits

System software can modify bits in this register, but the device is prohibited from

doing so.

If the device writes the same message multiple times, only one of those messages is

ensured to be serviced. If all of them must be serviced, the device must not generate

the same message again until the driver services the earlier one.

Bit

Access &

Default

Description

15:8

00h

Reserved

64-bit Address Capable (64AC): Hardwired to 0 to indicate that the

function does not implement the upper 32 bits of the Message Address

6:4

000b

Multiple Message Enable (MME): System software programs this

field to indicate the actual number of messages allocated to this

device. This number will be equal to or less than the number actually

requested.

The encoding is the same as for the MMC field below.

3:1

000b

Multiple Message Capable (MMC): System software reads this field

to determine the number of messages being requested by this device.

000 = 1 message requested

All others are reserved.

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