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82G33 Datasheet(PDF) 188 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 188 Page - Intel Corporation

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PCI Express* Registers (D1:F0)
188
Datasheet
6.1.7
CL1—Cache Line Size
B/D/F/Type:
0/1/0/PCI
Address Offset:
0Ch
Default Value:
00h
Access:
RW
Size:
8 bits
Bit
Access &
Default
Description
7:0
RW
00h
Cache Line Size (Scratch pad): Implemented by PCI Express
devices as a read-write field for legacy compatibility purposes but has
no impact on any PCI Express device functionality.
6.1.8
HDR1—Header Type
B/D/F/Type:
0/1/0/PCI
Address Offset:
0Eh
Default Value:
01h
Access:
RO
Size:
8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Bit
Access &
Default
Description
7:0
RO
01h
Header Type Register (HDR): Returns 01 to indicate that this is a
single function device with bridge header layout.
6.1.9
PBUSN1—Primary Bus Number
B/D/F/Type:
0/1/0/PCI
Address Offset:
18h
Default Value:
00h
Access:
RO
Size:
8 bits
This register identifies that this "virtual" Host-PCI Express bridge is connected to PCI
bus #0.
Bit
Access &
Default
Description
7:0
RO
00h
Primary Bus Number (BUSN): Configuration software typically
programs this field with the number of the bus on the primary side of
the bridge. Since device 1 is an internal device and its primary bus is
always 0, these bits are read only and are hardwired to 0.



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