82G33 datasheet(219/437 Pages) INTEL

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PCI Express* Registers (D1:F0)

Datasheet

219

6.1.43

SLOTSTS—Slot Status

B/D/F/Type:

0/1/0/PCI

Address Offset:

BA–BBh

Default Value:

0000h

Access:

RO, RWC

Size:

16 bits

PCI Express Slot related registers allow for the support of Hot Plug.

Bit

Access &

Default

Description

15:7

0000000b

Reserved and Zero: For future R/WC/S implementations; software

must use 0 for writes to bits.

Presence Detect State (PDS): This bit indicates the presence of an

adapter in the slot, reflected by the logical "OR" of the Physical Layer

in-band presence detect mechanism and, if present, any out-of-band

presence detect mechanism defined for the slot's corresponding form

factor. Note that the in-band presence detect mechanism requires that

power be applied to an adapter for its presence to be detected.

Consequently, form factors that require a power controller for hot-

plug must implement a physical pin presence detect mechanism.

0 = Slot Empty

1 = Card Present in slot

This register must be implemented on all Downstream Ports that

implement slots. For Downstream Ports not connected to slots (where

the Slot Implemented bit of the PCI Express Capabilities Register is

0b), this bit must return 1b.

Reserved

Command Completed (CC): If Command Completed notification is

supported (as indicated by No Command Completed Support field of

Slot Capabilities Register), this bit is set when a hot-plug command

has completed and the Hot-Plug Controller is ready to accept a

subsequent command. The Command Completed status bit is set as

an indication to host software that the Hot-Plug Controller has

processed the previous command and is ready to receive the next

command; it provides no assurance that the action corresponding to

the command is complete.

If Command Completed notification is not supported, this bit must be

hardwired to 0b.

RWC

Detect Changed (PDC): This bit is set when the value reported in

Presence Detect State is changed.

MRL Sensor Changed (MSC): If an MRL sensor is implemented, this

bit is set when a MRL Sensor state change is detected. If an MRL

sensor is not implemented, this bit must not be set.

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