82G33 datasheet(382/437 Pages) INTEL

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Electrical Characteristics

382

Datasheet

These rails are filtered from other voltage rails on the platform and should be measured at the

input of the filter. See the Platform Design Guide for proper implementation of the filter circuits.

VCCA_DAC voltage tolerance should only be measured when the DAC is turned ON and at a

stable resolution setting. Any noise on the DAC during power on or display resolution changes do

not impact the circuit.

MCH supports both Vtt=1.2V nominal and Vtt=1.1V nominal depending on the identified

processor.

11.4.2

General DC Characteristics

Platform Reference Voltages at the top of the following table are specified at DC only.

Vref measurements should be made with respect to the supply voltage. Customers

should refer to the Platform Design Guide for proper decoupling of the Vref voltage

dividers on the platform.

Table 11-6. DC Characteristics

Symbol

Parameter

Min

Nom

Max

Unit Notes

Reference Voltages

FSB_DVREF

FSB_ACCVREF

Host Data, Address, and

Common Clock Signal

Reference Voltages

0.666 x

VTT_FSB

–2%

0.666 x

VTT_FSB

0.666 x

VTT_FSB

+2%

FSB_SWING

Host Compensation Reference

Voltage

0.25 x VTT_FSB

–2%

0.25 x

VTT_FSB

0.25 x VTT_FSB

+2%

CL_VREF

Controller Link Reference

Voltage

0.270 x VCC_CL

0.279 x

VCC_CL

0.287 x

VCC_CL

DDR_VREF

DDR2/DDR3 Reference Voltage

0.49 x

VCC_DDR

0.50 x

VCC_DDR

0.51 x

VCC_DDR

Host Interface

VIL_H

Host GTL+ Input Low Voltage

-0.10

(0.666 x

VTT_FSB) - 0.1

VIH_H

Host GTL+ Input High Voltage

(0.666 x

VTT_FSB) + 0.1

VTT_FSB

VTT_FSB + 0.1

VOL_H

Host GTL+ Output Low Voltage

—

(0.25 x

VTT_FSB) + 0.1

VOH_H

Host GTL+ Output High Voltage VTT_FSB – 0.1

—

VTT_FSB

IOL_H

Host GTL+ Output Low Current

—

VTT_FSBmax *

(1-0.25) /

Rttmin

Rttmin =

47.5 Ω

ILEAK_H

Host GTL+ Input Leakage

Current

—

μA

VOL<

Vpad<

Vtt_FSB

CPAD

Host GTL+ Input Capacitance

2.0

—

2.5

CPCKG

Host GTL+ Input Capacitance

(common clock)

0.90

—

2.5

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