OR3TP12 datasheet(78/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

The read data phase will follow, by deassertion of taenn, assertion of Target read data enable (trdataenn). trda-

taenn can only be asserted while tr_fulln is deasserted, indicated that space is available in the read data FIFOs.

While trdataenn is asserted, the FPGA application will transfer Target read data on bus datafmfpga to the read

data FIFOs. The FPGA application is informed when the last component of the data phase is need when trlast-

cycn is asserted. In a burst access, this is during the last data phase. Assuming this is a burst access, (datatofp-

gax[1] = 1 during command/address phase), trlastcycn is deasserted during the read data phase except for the

last data of the read data phase. After receiving trlastcycn at the end of the data phase, trdataenn must be deas-

serted by the FPGA application. trlastcycn can only be asserted when trdataenn is asserted. See Read Data

Transfer section for details on trlastcycn.

For quad-port mode (Figure 32), the address data is transferred on the bus twdata in 16-bit segments. The

address will be split into two 16-bits components with the LSB being transferred first. A burst operation and dual-

address indication accompanies the address on twdata[17] and twdata[16] respectively. Assuming a BAR size

greater than 16 bits, the address phase will require two clock cycles for a 32-bit address, and twlastcycn will be

asserted on the final or MSB component of the address. The data phase will also require two clock cycles to trans-

fer every 32-bit read data word across the 16-bit bus trdata from the FPGA application. trlastcycn will be deas-

serted for all 16-bit components of the read data phase, except for the final 16-bit component where it is asserted.

5-7550(F)

Figure 33. Target Memory Burst Read, Nondelayed (PCI Bus, 32-Bit)

Tn0

Tn1

Tn2

Tn3

Tn4

ADDRESS

MEM RD

BE0

BE1

BE2

BE3

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

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