OR3TP12 datasheet(80/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed

Description (continued)

Clocking Options at FPGA/Embedded Core

Boundary

The OR3TP12 PCI bus core is divided into two clock

domains by two sets of dual-port FIFOs, one set dedi-

cated to each Target and Master function. The FPGA

supplies at least one clock, while the PCI bus provides

the second clock (clk).

The Master and Target FIFOs interface are always

independently clocked on the FPGA side by either

fclk1 or fclk2. The clocks used for the Master FIFO

and Target FIFO interfaces to the FPGA application

can be independent when the interface is configured in

quad-port mode, but they must use the same clock sig-

nal for dual-port mode. For dual-port, only one clock

port is active while the other is tied inactive.

All transfers to/from the FIFO interfaces are synchro-

nized to fclk1 and/or fclk2. Which port is used for syn-

chronization is decided by the FPSC configuration

manager for the Master and Target FIFO interfaces.

The

ORCA Foundry software will minimize the clock

skew between the FFs involved in the data transfers

and the appropriate synchronized clock port. The clock

delay from the clock source to the fclk1/2 port usually

does not affect transfer across the Master or Target

FIFO interface, since the interface is referenced from

the clock port (fclk1 or fclk2) and not the clock source

driver.

Figure 34 illustrates the special clock paths provided to

service the clocking needs of OR3TP12. The various

clocking options shown in Figure 34 are discussed

below.

PCI Clock as Interface Clock

The clock received from the PCI bus can be brought

across the embedded core into the FPGA logic section

and used as the clock for the entire OR3TP12, and

even as the clock for the entire board on which the

OR3TP12 resides. It is important that this signal be

obtained via the embedded PCI bus core only since

PCI rules allow for one load per agent on the PCI bus

clock. The OR3TP12 incorporates a clock tree for dis-

tributing the PCI clock; these lines are hard-connected

in the PCI bus core's circuitry and are passed up onto

the FPGA portion's clock grid. From there, the clock

can feed all PFUs, PIOs, fclk1, fclk2, and off-chip

resources.

Local Clock as Interface Clock

The FIFO interface between the PCI bus core and the

FPGA must use clocks sourced from the FPGA array.

The Master and Target FIFO interfaces each have inde-

pendent clock nets (fclk1/2) and can be connected to

the same or separate clocks. Both the Master and Tar-

get FIFO interface can be independently configured to

use any clock located in the FPGA, or provided exter-

nally.

The clocks for the Master and Target FIFO Interface are

fed from specific vertical clock spines, namely, the

spines in PLC columns five and 13. Consequently, min-

imum clock net delay is obtained by feeding external

clocks from I/O pads in locations on the top of the array

near these splines. Depending on which spline (fclk1

or fclk2) is used to distribute the clock to the Master

and Target FIFO Interface, it is recommended to use a

PIO that lies in that same column as the spline. For

fclk1 (which lies in column 13), use a PIO in PT13A-

PT14D. For fclk2 (which lies in column five), use a PIO

in PT5A-PT6D. If the user chooses the FAST_CLOCK

or EXPRESS_CLOCK as a source for the OR3TP12

clock, additional clock delay may be introduced. Never-

theless, clocks can be fed from any I/O pad, from

express clock inputs, or from internal logic, and can be

fed via the PCM.

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