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OR3TP12 Datasheet(PDF) 2 Page - Agere Systems |
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OR3TP12 Datasheet(HTML) 2 Page - Agere Systems |
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2 / 128 page  Table of Contents Contents Page Contents Page ORCA OR3TP12 FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 2 Lucent Technologies Inc. Introduction............................................................... 1 PCI Local Bus........................................................ 1 PCI Bus Core Highlights........................................... 1 FPSC Highlights ....................................................... 6 Software Support...................................................... 6 Description................................................................ 7 What Is an FPSC?................................................. 7 FPSC Overview..................................................... 7 FPSC Gate Counting............................................. 7 FPGA/Embedded Core Interface .......................... 7 FPSC Design Kit ................................................... 8 ORCA Foundry Development System................... 8 FPGA Logic Overview ........................................... 8 PLC Logic.............................................................. 9 PIC Logic............................................................... 9 System Features ................................................... 9 Routing ..................................................................10 Configuration .........................................................10 More Series 3 Information .....................................10 OR3TP12 Overview..................................................10 Device Layout........................................................10 OR3TP12 PCI Bus Core Overview...........................10 PCI Bus Interface ..................................................10 Embedded Core Options/FPGA Configuration......12 PCI Bus Core Detailed Description ..........................13 PCI Bus Commands..............................................13 PCI Protocol Fundamentals ..................................16 PCI Bus Pin Information ........................................18 Embedded Core/FPGA Interface Signal Descriptions ............................................21 Embedded Core/FPGA Interface Signal Locations.................................................29 Embedded Core Configuration Options ................31 Embedded Core/FPGA FIFO Interface Operation Summary ...........................................33 PCI Bus Core Master Controller Detailed Description ..............................................34 FIFO Interface Overview .......................................34 Master Write Operation .........................................35 Master Read Operation .........................................43 PCI Bus Core Target Controller Detailed Description .............................................. 53 Target FIFO Interface............................................ 53 Target Write Operation.......................................... 53 Target Read Operation.......................................... 65 Clocking Options at FPGA/Embedded Core Boundary ...................................................80 Configuration Space of the PCI Bus Core.............82 FPSC Configuration ..............................................86 FPGA Configuration Target Controller Data Format ..........................................................88 Using ORCA Foundry to Generate Configuration RAM Data ....................................88 FPGA Configuration Data Frame ..........................88 Bit Stream Error Checking ........................................90 FPGA Configuration Modes......................................90 Absolute Maximum Ratings......................................91 Recommended Operating Conditions ......................91 Electrical Characteristics ..........................................92 Timing Characteristics ..............................................93 Description................................................................93 PFU Timing .......................................................... 94 PLC Timing........................................................... 94 SLIC Timing.......................................................... 94 PIO Timing ........................................................... 94 Special Function Timing ........................................94 Clock Timing .............................................................94 Configuration Timing .............................................94 Readback Timing ................................................. 94 Input/Output Buffer Measurement Conditions ..........99 Output Buffer Characteristics ................................. 100 Estimating Power Dissipation ................................. 101 Pin Information ....................................................... 102 ΘJA......................................................................119 ψJC......................................................................119 ΘJC......................................................................119 ΘJB......................................................................119 FPGA Maximum Junction Temperature .............. 119 Package Thermal Characteristics........................... 120 Package Coplanarity .............................................. 120 Package Parasitics ................................................. 120 Package Outline Diagrams..................................... 122 Terms and Definitions ......................................... 122 240-Pin SQFP2 ................................................... 123 256-Pin PBGA ..................................................... 124 352-Pin PBGA ..................................................... 125 Ordering Information............................................... 126 |
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