OR3TP12 datasheet(59/128 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3TP12 FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Target Controller Detailed Description (continued)

Target Write Memory, Single-Word Transaction

Figure 17 shows the timing on the PCI bus, for a Target memory write of a single word. The timing on the PCI inter-

face (Figure 17) is similar to that of a posted I/O write (Figure 16) except that, since bursts to memory space are

allowed, the signal stopn is not asserted.

5-7373(F)

Figure 17. Target Memory Single Write (PCI Bus, 32-Bit)

Single Target Write FIFO Interface

The FIFO interface timing is as shown in Figure 18 and Figure 19 for dual- and quad-port respectively. The inter-

face timing is similar for all Target I/O writes and Target single memory writes, since the Target FIFO interface is

uniform across all Target accesses.

The timing on the interface (Figure 18 for dual-port) shows the first indication to the FPGA application that a new

operation is pending by the assertion of Target request (treqn). When treqn is valid, the FPGA application begins

the command/address phase by asserting Target address enable (taenn) and accepting the command from bus

tcmd and address from bus datatofpga(x) (with fifo_sel = 1). If applicable, the dual-address indication bit accom-

panies the address on datatofpga[0], whereas for the single access on a 32-bit PCI bus (pci_64bit = 0) the burst

indication bit (datatofpga[1]) will be desasserted. The FPGA application continues to receive new address data

(taenn asserted) on every clock until twlastcycn is asserted, indicating the end of the command/address phase.

See command/address section for notes regarding address transfer and alignment.

The write data phase will follow, by deassertion of taenn, and assertion of Target write data enable (twdataenn).

twdataenn can only be asserted while tw_emptyn is deasserted, indicating that write data is available in the write

data FIFOs. While twdataenn is asserted, the FPGA application will receive Target write data on bus datatofpga

(with fifo_sel = 1). The FPGA application is informed that the last component of the data phase is being presented

when twlastcycn is asserted. Since this is a single access on a 32-bit data bus (assuming datatofpgax[1] = 0 dur-

ing command/address phase, pci_64bit = 0), the first and only data phase is the last data of the write data phase.

ADDRESS

DATA

MEM WR

BYTE ENABLES

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

OR3TP12 Datasheet(PDF) 59 Page - Agere Systems

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