OR3TP12 datasheet(34/128 Pages) AGERE

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ORCA OR3TP12 FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Master Controller

Detailed Description

FIFO Interface Overview

The Master FIFO interface consists of two transfer

phases: command/address followed by data. This

sequence must be followed, with the assertion of

mwlastcycn indicating the completion of each phase.

In both quad- and dual-port modes, the command is

transferred first, followed by address, then data. The

PCI start address and bus command are always pro-

vided by the FPGA application. For Master writes, write

data with byte enables will be provided by the FPGA

application, whereas for reads the Master will receive

its data from the PCI bus and forward on to the FPGA

application. All types of data are transferred on the data

paths defined by the operational mode (dual- or quad-

port).

Master State Counter

The Master FIFO interface provides a state counter,

mstatecntr[3:0], that informs the FPGA application of

its current state (Table 12). This state counter deter-

mines what data is expected from the FPGA applica-

tion during the command/address or write data phases,

or what is currently being provided by the Master FIFO

interface during read data phases. This state counter

transitions from one state to another in a predeter-

mined manner. Table 13 through Table 17 detail the

sequencing of the mstatecntr and the data transferred

for Master write and read transactions.

The value on bus mstatecntr can be used to minimize

FPGA logic or verify proper operation. The data pro-

vided by the Master FIFO interface to the FPGA appli-

cation is accompanied by a value on mstatecntr[3:0],

as shown in Table 12. This value can be directly used

by the FPGA application to determine the proper orien-

tation of the Master read data. This eliminates the need

for logic in the FPGA application for possible data pack-

ing functions. The data required from the FPGA appli-

cation by the Master FIFO interface during the

command/address or write data is also defined by the

value on mstatecntr. However, the state counter value

being presented to the FPGA application is in the same

cycle that the data is sent from the FPGA. Here, the

value provided by the Master FIFO interface can be

used to determine the next state, since current data,

phase, enables, and state transitions is known.

Dual-Master Address Holding Registers

The Master FIFO interface utilizes a pair of 64-bit

address holding registers to reduce latency when set-

ting up repeated Master transfers to or from the same

PCI address. Every Master command/address phase

has associated with it one of the two holding registers,

as specified by the holding register selector (Master

command word bit 12, as described in Table 10). Each

address holding register records the full previous

address, allowing some, all, or none of that recorded

address to be used to build the next address associ-

ated with that holding register. This can save up to 2/4

cycles (for dual-port/quad-port mode, respectively) dur-

ing the command/address phase.

The holding register supplies the most significant por-

tion, or all, or none, of the address. The amount sup-

plied by the holding register is determined by the timing

of the signal mwlastcycn, which accompanies the last

portion of data during the command/address phase. If

mwlastcycn accompanies the Master command word,

the holding register supplies the entire address. Table

11 gives examples of typical operation using the hold-

ing registers, illustrating the above rules.

The holding registers can be partitioned using one

each for read and write operations, thus providing two

unrelated addresses for two functions. Another useful

application is to dedicate one holding register to a fixed

address such as the beginning of a buffer, the data port

of a FIFO or a mailbox register. This increases effective

bandwidth on shorter bursts.

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